The ever-increasing miniaturization in integrated circuits has rendered it possible to integrate entire systems in a single silicon crystal. It has now become desirable in this development to combine memories with the logic usual in, for example, CMOS technology. These memories are often called "embedded memories" in the literature. A type of memory which is of particular importance in this connection is the non-volatile memory or EPROM (Electrically Programmable Read Only Memory). The memory element is formed by a transistor with a floating gate whose threshold voltage is determined by the written information in the form of electric charge on the floating gate electrode. The control gate on the one hand serves to detect what the threshold voltage, and thus the written information is during reading and on the other hand to influence the potential of the floating gate during writing and/or erasing.
A method of the kind mentioned in the opening paragraph is known inter alia from US Pat. No. 4,719,184. In this known process, the non-volatile memory element is manufactured with two layers of polycrystalline silicon (called poly hereinafter for short) mutually separated by a dielectric, for example an oxide, the floating gate being formed from the lower poly layer and the control gate from the upper poly layer. The normal transistors of the logic gates are manufactured from the same poly layers, obviously without the inter-poly dielectric, and in the same process steps as the memory elements. It is generally desirable for non-volatile memories that writing and/or erasing can take place at a reasonable speed and at comparatively low voltages (for example, below 15 V) which can be readily generated in the circuit itself. If this means that certain process conditions are to be fulfilled, it is usual to adapt the process for the normal CMOS logic to this in order to keep the process as simple as possible. This may lead to problems. Especially with channel lengths below 1 .mu.m, the use of an optimized process for the memory may thus easily lead to degradation in the logic transistors because the injection of charge carriers into the gate dielectric will shift the threshold voltage in the course of time. Summarizing, the optimization of the "embedded" EPROM is difficult to realise when the dimensions in the logic become small, in particular in the case of channel lengths below 1 .mu.m.